The following analyses are given by the present invention.
Such a semiconductor memory device that comprises a cell array formed by dynamic type memory cells in need of refresh for data retention, and that is adapted to operate as a static random access memory (SRAM), has so far been in use. This type of the semiconductor memory is also termed a pseudo SRAM or a pseudostatic DRAM. There have also been developed a RAM family (termed for example MSRAM) for use of a mobile application, which is functionally compatible with the low power SRAM and which has achieved a high storage capacity by exploiting DRAM memory cells (see Non-Patent Document 1, indicated hereinbelow). With the pseudostatic DRAM, it is unnecessary to separately supply a row address and a column address, as an address, as is done in the case of a DRAM, and hence timing signals, such as RAS (row address strobe) or CAS (column address strobe) are unneeded. The semiconductor memory device of the family of the pseudostatic DRAM includes a timer for prescribing a refresh period, and a refresh address generator, and refresh is carried out by a trigger signal generated responsive to timeout of a timer. That is, the refresh operation is carried out with a preset time interval by the timer, while the timing for generation of the refresh operation usually cannot be controlled from outside. The following explanation is made on the basis of the description of the Patent Document 1.
In the pseudostatic DRAM, the self-refresh operation which is controlled by a timer, and the read/write operation which is non-periodically generated responsive to a signal entered from outside the device, occur independently of each other, such that the time durations of the two operations usually cannot be controlled from outside the device. In a well-known manner, if the self-refresh operation is temporally overlapped with the read/write operation, malfunctions are produced. These malfunctions may be exemplified by destruction of data for retention, in the case of the refresh operation, and by reading/writing of erroneous data in the case of the read/write operations. For preventing these malfunctions from occurring, such measures are taken in which, if a request of a second operation should be issued while a first operation is being carried out, the second operation is not started, but is kept to be in a wait state, until the first operation, already started, comes to a close.
For example, if a read request (read command) is issued in the course of a self-refresh operation, the read operation is not carried out for the time being and is kept in a wait state, with the read operation being carried out after the end of the self-refresh operation.
However, if the timing of generation of the self-refresh operation is close to that of the read/write operation, malfunctions may possibly be produced by interference between the operations.
Examples of these malfunctions include:
    (A) interference between word lines    (B) insufficient pre-charge ascribable to shorter time durations between the operations    (C) the pulse signal generated in one operation disturbing the other operation
Thus, before product shipment of the semiconductor memory device, it is necessary to carry out testing of the semiconductor memory device for checking an operation in such a condition where the self-refresh operation and the readout/write operation come close.
For coping with this problem, the Patent Document 1 discloses a method for controlling a semiconductor memory device having a plural number of memory cells that are in need of refresh for data retention, in which the timing of the refresh operation for the normal operation mode is set with the timing of generation of a refresh control signal, generated within the semiconductor memory device, as a trigger, and in which the timing of the refresh operation for the test operation mode is set, with a detection signal detecting a change in the state of an external input signal, as a trigger, so that the timing offset of the timing of the refresh operation from the timing of the read/write operation will be equal to the timing offset as set from outside.
There is also known a configuration of a semiconductor memory device employing DRAM cells and having specifications comparable to those of an SRAM, in which there is provided a WAIT pin for suspending the access from outside during execution of the internal refresh, and in which there is provided the function of handshaking with the CPU (central processing unit) via this WAIT pin (see Non-Patent Document 2, indicated hereinbelow).
FIG. 4 shows a typical configuration of a conventional semiconductor memory device (pseudostatic DRAM), including dynamic type memory cells, in need of refresh for data retention, and which is provided with the handshaking function (WAIT pin), with the device carrying out the self-refresh operations.
Referring to FIG. 4, the semiconductor memory device includes a cell array core 100, and a data I/O register 115. The cell array core includes a memory array 101, an address decoder 102 (a row address decoder and a column address decoder), and a sense amplifier/write amplifier 103. The data I/O register 115 holds input/output data for a data terminal DQ and sends write data from a data bus to the cell array core 100, while receiving read data from the cell array core 100 to output the so received data at the data terminal. The semiconductor memory device also includes a register 111 for holding an address signal, entered from an address terminal ADD, a register 112 for holding a chip select command CS, a register 113 for holding a read/write command, a register 114 for holding and outputting a WAIT signal which is output from a WAIT pin, not shown, a timer 116 which determines a refresh period, an SR flip-flop 117 which is set by a trigger signal, output on time-out of the timer 116, to output a refresh request signal in an activated state, a refresh pulse generator 118′ which generates a refresh pulse signal REF responsive to the refresh request signal from the flip-flop 117, a refresh address generator 119 which generates a refresh address responsive to the refresh pulse signal REF, and a multiplexer 120 which outputs the refresh address or the input address supplied from the register 111 as a row address to the address decoder 102 (row address decoder). In addition, the semiconductor memory device includes an internal timing control circuit 121′ which generates signals for controlling various timing operations of the semiconductor memory device, a read/write control circuit 122 which receives a read/write command from the register 113 to control the read/write operation, a WAIT signal generator 123 which receives signals from the internal timing control circuit 121′ to generate a WAIT signal in case of occurrence of overlap of the refresh and the read/write request, a read/write pulse generator 124 which receives signals from the read/write control circuit 122 and from the internal timing control circuit 121′ to generate a read/write pulse R/W, and a controller 125 which receives the read/write pulse R/W from the read/write pulse generator 124 and the refresh pulse signal REF from the refresh pulse generator 118′ to generate a row enable signal RE, and controls the activation of a row-related component, for example, a selected word line, a sense enable signal SE for activating a sense amplifier, and a column enable signal CE for controlling the activation of a column-related component. In FIG. 4, CLK denotes an internal clock signal which is generated from an external clock signal for synchronization entered to the semiconductor memory device.
If, in the semiconductor memory device, a read/write command has been established (by the rising edge of the clock signal), and there is no refresh request, a read/write access is carried out, with a burst length being 8.
FIG. 5 depicts a timing diagram showing the operation of the semiconductor memory device at this time. In FIG. 5, CLK is a clock signal for synchronization, an ADD-R/W command is an address signal plus a read/write command, Refresh request is a refresh request signal, output from the SR flip-flop 117, Refresh inhibit is a refresh inhibit signal, supplied from the internal timing control circuit 121′ to the refresh pulse generator 118′, Core(Word) is a selected word line of the cell array core, R/W is a pulse waveform of the selected word line of the read/write access and Refresh is a pulse waveform of the selected word line corresponding to the refresh address.
In the example shown in FIG. 5, a read/write command is sampled by the register 113, while an address A0 is sampled into the register 111, at a timing t0, with the rising edge of the clock signal CLK. At this time, there is no refresh request, and the selected word line of the cell array core is activated, and hence for example, a read operation is carried out. By a read/write command input, a refresh inhibit signal from the internal timing control circuit 121′ is activated to inhibit the refresh. That is, no refresh pulse is generated in the refresh pulse generator 118′, supplied with the refresh inhibit signal in the activated state, and hence refresh is not executed and read/write accessing is carried out. Read-out data signals Q(0)-Q(7), with the burst length of 8, are output from the data terminal DQ, with the latency of ‘3’, that is, from the clock cycle of the timing t3. Meanwhile, in the example shown in FIG. 5, the data signals Q(0)-Q(7) are output in synchronization with the rising and falling edges of the clock signal CLK.
The refresh pulse generator 118′ (see FIG. 4), carrying out the control operation shown in FIG. 5, includes a gating circuit, such as AND circuit, not shown, which receives a refresh request signal from the flip-flop 117, and a signal obtained by inverting the refresh inhibit signal from the internal timing control circuit 121′, and a one-shot pulse generator, also not shown, adapted for generating a one-shot pulse responsive to transition of the output of the gating circuit to an activated state, for example, to a high level. The internal timing control circuit 121′ activates the refresh inhibit signal to a high level in case either the refresh pulse REF or the output of the register 113 (read/write access request) is in the activated state (high level). If the read/write access request is not processed and the refresh request is made first, the refresh inhibit signal is set to the activated state and kept in the activated state until the read/write operation is finished, even after the end of the refresh. In the examples shown in FIGS. 5 and 6, the internal timing control circuit 121′ is configured for resetting the refresh inhibit signal from the activated state (high level) to the inactivated state (low level) by the coming to a close of the read/write operation, that is, by transition from the high level to the low level of the read/write pulse.
If, during the read/write accessing, the time out occurs in the timer 116, the refresh request is generated, and the refresh inhibit signal is in the activated state (high level), the refresh pulse generator 118′ masks the input refresh request, and hence the refresh request pulse REF is not generated.
If, with a delay from the read/write operation (with the R/W pulse then going low from high), a refresh request is generated, the refresh operation is carried out. That is, when the time out occurs in the timer 116 (see ‘Timer’ of the ‘refresh request’ of FIG. 5), the flip-flop 117 is set, so that the refresh request is set to an activated state (high level). Since the refresh inhibit signal is in the inactivated state (low level) at this time, the refresh pulse generator 118′, which receives the refresh request signal in the activated state as an input, outputs the refresh pulse REF and the refresh address from the refresh address generator 119 is supplied to the address decoder 102 to carry out the refresh. The refresh inhibit signal is also set to the activated state, responsive to activation of the refresh pulse REF, by the internal timing control circuit 121′. When the refresh has come to a close, that is, when the refresh pulse REF undergoes transition from the activated state (high level) to the inactivated state (low level) (see the falling transition of the ‘Refresh’ of the Word in FIG. 5), the refresh inhibit signal is set by the internal timing control circuit 121′ to the inactivated state (low level). The flip-flop 117 is also reset, so that the refresh request signal is also reset.
If, in the semiconductor memory device, shown in FIG. 4, the refresh precedes the read/write command, the latency is ‘5’. The following explanation, made with reference to FIG. 6, is relevant to this semiconductor memory device.
Referring to FIG. 6, when the timer 116 has timed out (see ‘Timer’ of ‘Refresh request’ of FIG. 6), the refresh request signal is activated (goes high). Since the refresh inhibit signal is in the inactivated state (low level), the refresh pulse generator 118′ generates the refresh pulse REF to carry out the refresh operation. The internal timing control circuit 121′ sets the refresh inhibit signal to the activated state (high level). If the read/write command is entered at a timing t0 of FIG. 6, the read/write operation is in a wait state until the end of the refresh operation. After the refresh operation has come to a close, the read/write operation is carried out in the cell array core 100, and data is output at the data terminal DQ with the latency 5. If the refresh precedes the read/write, as shown in FIG. 6, the refresh inhibit signal is set to the activated state (high level), until the end of the read/write operation, even after the end of refresh, and is reset to an inactivated state (goes low) with the end of the read/write operation.
Thus, the latency is ‘3’ and ‘5’ if the read/write precedes the refresh and if the refresh precedes the read/write, respectively, such that there is caused the difference in the readout data output timing.
On the other hand, if the refresh temporally interferes with a read/write access, a WAIT signal in the activated state is output and a WAIT command for setting the WAIT state until the end of refresh is issued to the controller or to the CPU.
[Patent Document 1]
JP Patent Kokai No. JP2003-178598A
[Non-Patent Document 1]
NEC memory product information, mobile specified RAM, Internet <URL:http://www.necel.com/memory/japanese/products/msram/info.html>
[Non-Patent Document 2]
MICRON 4MEGx16, 2MEGx16 ASYNC/PAGE/Burst CellularRAM MEMORY, pages 5 and 10, Internet <URL:http://download.micron.com/pdf/products/psram/burst_cellularram.pdf>